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TITLE
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BukitTimahTutor ILT × InterstellarCore × ChronoFlight Education Corridor Control Tower v1.0
(Bukit Timah Schools → PSLE → PG1/PG2/PG3 → Secondary/FullSBB → IP/IB/Intl → JC/Poly/ITE → University → Career)
SLUG
bukit-timah-ilt-interstellarcore-chronoflight-education-corridor-control-tower-v1-0
VERSION
BT_ICF_CORRIDOR_CTW_v1_0
MODE
Almost-Code / WordPress paste-ready / LLM-ingestion stable spec
SCALE
Dual (Human ↔ District ↔ Nation bind) using Bukit Timah OS coordinates
DOMAIN
EducationOS + TuitionOS + ILT (Invariant Ledger Teaching) + InterstellarCore + ChronoFlight
CHRONOFLIGHT_LENS (LOCK)
Structure × Phase × Time
(Time slices: weekly; Gate approach: monthly→weekly→daily; Near-node compression rules apply)
PRIMARY_LOCAL_NODE (tuition execution)
BT.EDU.Z1.N.TUI.001
CONTROL_TOWER_COORDINATE (root)
BT.EDU.Z1.S.CTW.COR.ICF.001
DEPENDENCIES (do not rename)
- Bukit Timah Lattice Coordinate Standard v1.1
- Bukit Timah Seed Lattice v0.1
- Bukit Timah Tuition OS
- ILT v1.0 (Invariant Ledger Teaching) as operator-side method
- InterstellarCore definition lock (P3 corridor education runtime + GeniusCorridor release valve)
- ChronoFlight overlay lock (Structure × Phase × Time)
LOCAL_BINDS (Bukit Timah OS coupling)
- BT.FAM.Z0.P.LIF.001        # Household Life Pipeline
- BT.FAM.Z0.S.TTC.001        # TTC + friction + schedule sensors
- BT.TRN.Z2.B.MRT.DTL.06A    # Sixth Avenue
- BT.TRN.Z2.B.MRT.DTL.07A    # Tan Kah Kee
- BT.EDU.Z2.P.SCH.001        # PRI→SEC→PostSec pipeline (district)
- BT.EDU.Z2.N.KDG.001        # Kindergarten cluster node (placeholder)
- BT.EDU.Z2.N.PRI.001        # Primary cluster node (placeholder)
- BT.EDU.Z2.N.SEC.001        # Secondary cluster node (placeholder)
- BT.EDU.Z2.N.PST.001        # Post-secondary cluster node (placeholder)
- BT.EDU.Z2.N.UNI.001        # University cluster node (placeholder)
- BT.CAR.Z2.N.WRK.001        # Career / work corridor node (placeholder)
EXTERNAL_GATES (national / exam / selection binds)
- SG.EDU.Z6.N.EXM.PSLE.001   # PSLE gate node
- SG.EDU.Z6.N.GATE.PG.001    # Posting Group selection gate (PG1/PG2/PG3)
- SG.EDU.Z6.N.EXM.SEC.001    # SEC gate node (Secondary Education Certificate)
- SG.EDU.Z6.N.GATE.PST.001   # Post-secondary selection gate (JC/Poly/ITE/IB/Intl)
- SG.EDU.Z6.N.GATE.UNI.001   # University selection gate
- SG.CAR.Z6.N.GATE.001       # Career entry / role-fit gate
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0) CLASSICAL FOUNDATION BLOCK (baseline alignment; non-controversial)
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BASELINE:
- Education systems are progression systems: curriculum → instruction → assessment → feedback → advancement.
- Reliable progression requires: (a) clear learning outcomes, (b) formative feedback loops, (c) mastery checks, (d) remediation, (e) transfer practice.
- “Control tower” framing: a monitoring + intervention layer that keeps learners within a safe performance envelope across time.
THIS SPEC EXTENDS BASELINE BY:
- Making invariants explicit (ILT),
- Making Phase stability explicit (InterstellarCore = P3 corridor),
- Adding time-axis routing with near-node compression (ChronoFlight).
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1) AI EXTRACTION BOX (Google/LLM lock; paste-friendly)
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ONE-SENTENCE DEFINITION (LOCK):
BukitTimahTutor’s ILT–InterstellarCore–ChronoFlight Control Tower is a district-linked, time-aware education flight system that makes learning invariants visible (ILT), keeps every learner inside a Phase-3 stability corridor (InterstellarCore), and routes them across gates (PSLE→PG→SEC→PostSec→Uni→Career) using ChronoFlight sensors so RepairRate ≥ DriftRate under load.
NAMED MECHANISMS (LOCKED BULLETS):
- ILT (Invariant Ledger Teaching): teacher/system makes invariants visible + enforceable.
- InterstellarCore: P3 corridor runtime (stable learning under load) + GeniusCorridor (elite release valve).
- ChronoFlight: Structure×Phase×Time routing; near-node compression; time-to-threshold control.
- Ledger of Invariants: explicit checklist of what must stay true for competence to persist.
- VeriWeft (VWeft): validity fabric ensuring steps/relations remain admissible (no “fake” learning).
- Truncation + Stitching: smallest repair that restores corridor width without overload.
- Gate Mode: formal selection/exam gates; performance must land under gate conditions.
FAILURE MODE TRACE (required):
Z0 invariant leak → Z2 drift accumulates → near-node compression closes exits → P1 collapse under time → gate failure → buffer loss spiral → harder repair later.
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2) CIVILISATION-GRADE DEFINITION (expanded)
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DEFINITION (LOCK):
This Control Tower is a closed-loop corridor runner for Bukit Timah:
(1) instruments learner state (skills + transfer + metacognition + buffer),
(2) logs drift early (before “identity failure”),
(3) runs ILT to expose invariants and enforce correct forms,
(4) maintains P3 stability (InterstellarCore) across weekly time slices,
(5) routes the learner through institutional gates (PSLE/PG/SEC/PostSec/Uni/Career),
(6) prevents near-node debt (ChronoFlight) by cutting overload and proving landings.
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3) CANONICAL FRAMING BOX (placement + invariants)
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PLACE: BT
LANE: EDU (with CAR binds)
ZOOM_BANDS:
- Z0 micro-skill
- Z1 tutor/student execution loop
- Z2 district school + household coupling
- Z6 national gates (PSLE/SEC/PostSec/Uni/Career)
PHASE GAUGE:
P0 unsafe/random
P1 scaffolded; prompt-dependent
P2 independent; syllabus-stable
P3 robust under time + transfer + self-correction (target corridor)
MASTER LAW:
RepairRate ≥ DriftRate (especially under load)
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4) CORRIDOR MAP (END-TO-END ROUTE GRAPH)
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ID: BT_ICF_ROUTE_GRAPH_01
STAGES (human-facing):
S0 Kindergarten
S1 Primary (P1–P6) + PSLE
S2 Posting Group selection (PG1/PG2/PG3)
S3 Secondary (Full SBB G1/G2/G3) + SEC
S4 Track forks: IP / IB / International School / JC / Poly / ITE
S5 University
S6 Career (role-fit + stability + progression)
CANONICAL NODES (machine):
BT.EDU.Z2.N.KDG.001  -> BT.EDU.Z2.N.PRI.001 -> SG.EDU.Z6.N.EXM.PSLE.001
-> SG.EDU.Z6.N.GATE.PG.001 -> BT.EDU.Z2.N.SEC.001 -> SG.EDU.Z6.N.EXM.SEC.001
-> SG.EDU.Z6.N.GATE.PST.001 -> BT.EDU.Z2.N.PST.001 -> SG.EDU.Z6.N.GATE.UNI.001
-> BT.EDU.Z2.N.UNI.001 -> SG.CAR.Z6.N.GATE.001 -> BT.CAR.Z2.N.WRK.001
TRACK FORKS (within stage S4):
- BT.EDU.Z2.N.SEC.IP.001        # IP corridor (placeholder)
- BT.EDU.Z2.N.SEC.IB.001        # IB corridor (placeholder)
- BT.EDU.Z2.N.SEC.INTL.001      # International School corridor (placeholder)
- BT.EDU.Z2.N.PST.JC.001        # Junior College corridor (placeholder)
- BT.EDU.Z2.N.PST.POLY.001      # Polytechnic corridor (placeholder)
- BT.EDU.Z2.N.PST.ITE.001       # ITE corridor (placeholder)
FULL SBB (within Secondary):
- SEC subjects run by level: G1 / G2 / G3 (corridor lanes; not a “label”)
- Local runtime must support mixed level subjects without identity collapse.
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5) CONTROL VARIABLES (CHRONOFLIGHT STATE X(k))
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ID: BT_ICF_CF_STATE_01
STATE PER TIME SLICE k:
X(k) = {
 τ    : TTC_to_next_gate (time-to-gate, weeks),
 A    : ExitAperture (options left; reversibility),
 B    : Buffer (sleep/energy/time/attention),
 S    : Signal (true mastery evidence),
 N    : Noise (test noise, stress noise, copied work, false stability),
 R    : RepairRate (skill recovery velocity),
 D    : DriftRate (forgetting + error growth velocity),
 Δt_b : TimeDebt (borrowed time from sleep/health/other subjects),
 W    : AVOO weights (Architect/Visionary/Oracle/Operator mix by node distance)
}
TRUTH CLARITY:
TruthClarity = S / (S + N)
ROUTE CLASSIFIER (lattice band):
+Latt (stable) if TruthClarity≥θ_s AND R≥D AND A>A_min AND B>B_min
0Latt (boundary) if near thresholds
-Latt (unstable) if A≤A_min OR B≤B_min OR (R<D under load) persists
NEAR-NODE COMPRESSION LAW:
as τ→0:
A ↓ , B ↓ , reversal_cost ↑
therefore wrong decisions appear plausible if debt is high and exits are closed.
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6) ILT INSTALLATION (OPERATOR-SIDE MODULES; SAME AT ALL STAGES)
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ID: BT_ILT_INSTALL_PACK_01
ILT IS WHAT THE TEACHER/SYSTEM DOES (operator), NOT WHAT THE CHILD “WANTS”.
MODULES (operator-side; stable):
ILT-M1 Invariant Visibility:
- make “what must stay true” explicit (steps, definitions, units, constraints, grammar of solutions)
ILT-M2 Reconciliation:
- compare student output to invariant ledger; show exactly where reconciliation breaks
ILT-M3 Breach Detection:
- detect breach early (repeat error buckets, missing step types, prompt dependence)
ILT-M4 Repair Routing (truncate+stitch):
- route to smallest Z0 repair corridor; ban “topic binge”
ILT-M5 Transfer Bridge:
- practice invariant under variation (new surface forms); prove generalisation
ILT-M6 Ledger Logging:
- update ledger entries + breach history + retest schedule
ILT-M7 Load Proof:
- timed mini-landings; verify stability under real load
ILT OUTPUT FORMAT (every week):
- Invariant Ledger (Top 10)
- Breach List (Top 3)
- Repair Queue (Top 5)
- Next Retests (D+1/D+3/D+7/D+14/D+30)
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7) INTERSTELLARCORE INSTALLATION (P3 CORRIDOR RUNTIME)
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ID: BT_INTERSTELLARCORE_RUNTIME_01
INTERSTELLARCORE (LOCKED DEFINITION):
Phase-3 corridor education runtime across Z0–Z6, with a bounded GeniusCorridor
(Architect-grade release valve) that returns artefacts to the base.
P3 REQUIREMENTS (must be true):
- RepairRate ≥ DriftRate under load
- Proof under time (landing tests)
- Buffer not cannibalised (BaseFloor protected)
- Verification signals exist (not vibe-based)
GENIUSCORRIDOR (bounded):
- for high-capacity learners: deeper problem spaces, research/olympiad, creation
- must not steal repair capacity from base population
- must return tools/artefacts back into P3 base (notes, methods, checklists)
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8) THE ONE-PANEL CORRIDOR DASHBOARD (WEEKLY)
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ID: BT_ICF_ONE_PANEL_01
PANEL A — ROUTE STATE:
Stage (KDG/PRI/PSLE/PG/SEC/PostSec/Uni/Career)
Phase (P0–P3)
RouteState (climb/stable/drift/corrective/descent)
PANEL B — GATE PROXIMITY:
NextGate
τ (weeks)
Θ (irreversibility ratio)
A (exit aperture estimate)
PANEL C — STABILITY EVIDENCE:
TruthClarity
TimedLandingScore
TransferScore
RepeatBucketIndex (ECI)
PANEL D — BUFFER / TTC:
Sleep band
Weekly load band
TTC friction index
Δt_b (time debt)
PANEL E — ACTIONS (outputs):
Top 2 repairs (truncate+stitch)
1 timed landing (age-appropriate)
3 micro-maintenance returns
1 transfer bridge set
Parent envelope action (reduce friction)
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9) STAGE-SPECIFIC GATE RUNTIMES (WHAT CHANGES BY STAGE)
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ID: BT_ICF_STAGE_RUNNER_01
STAGE S0 — Kindergarten (KDG)
Primary objective:
- readiness invariants (attention, counting sense, language of instruction, routines)
ILT ledger examples:
- “I can follow a 2-step instruction”
- “I can represent quantity”
ChronoFlight:
- B (buffer) is the main constraint; keep sessions short, frequent, kind.
STAGE S1 — Primary (P1–P6) + PSLE
Primary objective:
- build MPS (problem solving) + representation invariants + timed stability near PSLE
Gates:
- PSLE format landings; Paper 1 no-calc discipline; Paper 2 working rent
ILT ledger:
- model → method → compute → check; units; estimation; bar model invariants
STAGE S2 — PG Selection (PG1/PG2/PG3)
Primary objective:
- prevent identity collapse from placement outcome; route to repair corridor fast
ILT:
- ledger does NOT change; corridor width changes; repair becomes priority
ChronoFlight:
- τ resets; choose a stable corridor, not an ego corridor.
STAGE S3 — Secondary + Full SBB (G1/G2/G3) + SEC
Primary objective:
- maintain multi-subject stability; handle mixed levels; prove timed landings
ILT:
- per-subject ledger + shared metacognition ledger (checking, method selection)
InterstellarCore:
- base P3 corridor for all; optional GeniusCorridor for high-capacity
STAGE S4 — Track Forks (IP/IB/Intl/JC/Poly/ITE)
Primary objective:
- route-fit + survivability + future mobility
ILT:
- invariants become track-specific (e.g., IA/EE, project work, practicals)
ChronoFlight:
- “exit aperture” planning matters; keep options open with stable fundamentals.
STAGE S5 — University
Primary objective:
- self-directed learning + proof of competence via projects/exams
ILT:
- convert into self-ILT: learner learns to keep their own ledger
STAGE S6 — Career
Primary objective:
- role-fit + performance stability + growth without burnout
InterstellarCore:
- lifelong P3 corridor; optional P4 frontier windows (bounded) if surplus exists
ChronoFlight:
- continuous routing; detect drift before job collapse.
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10) ROUTING RULES (DECISION ENGINE; NON-PERSUASIVE)
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ID: BT_ICF_ROUTING_RULES_01
RULE R1 (Safety first):
If B < B_min OR Θ < 1 → reduce load; repair only; postpone novelty.
RULE R2 (Truth over vibes):
If timed landing fails repeatedly → treat as unstable, regardless of homework grades.
RULE R3 (Two-bucket repair):
Repair TOP 2 repeat buckets only each week; over-repair creates new drift.
RULE R4 (Transfer required):
If TR below threshold → add variation ladder; ban template-only training.
RULE R5 (Gate approach):
As τ shrinks, stop exploration; increase landings + maintenance; preserve buffer.
RULE R6 (Track fit):
Prefer stable corridor with future mobility over fragile prestige corridor.
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11) DISTRICT SCHOOL / AREA BINDING (BUKIT TIMAH “SCHOOLS MAP” LAYER)
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ID: BT_SCHOOL_MAP_LAYER_01
PURPOSE:
Link this corridor control tower to actual Bukit Timah institutions without hardcoding names here.
SCHEMA (placeholders; fill via registry page later):
BT.EDU.Z2.N.KDG.SCH.<ID>
BT.EDU.Z2.N.PRI.SCH.<ID>
BT.EDU.Z2.N.SEC.SCH.<ID>
BT.EDU.Z2.N.PST.SCH.<ID>
BT.EDU.Z2.N.UNI.SCH.<ID>
ALIAS REGISTRY (separate page recommended):
- school official name
- common name variants
- program types (IP/IB/Intl/FullSBB)
- travel binds (MRT/bus)
- load profile notes
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12) VERSION LOCK + UPGRADE PROTOCOL
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BT_ICF_CORRIDOR_CTW_v1_0
RULES:
- Coordinates follow: <REGION>.<LANE>.Z<ZOOM>.<ROLE>.<TYPE>.<ID>
- ILT modules are operator-side only (do not reframe as “student motivation”)
- InterstellarCore = P3 corridor runtime; GeniusCorridor bounded + artefact return
- ChronoFlight state variables remain stable (τ,A,B,S,N,R,D,Δt_b,W)
- Forward-only upgrades; keep MetricIDs stable
END.

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CHILD PACK 1/3 — BT SCHOOL MAP & REGISTRY SPEC v1.0
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TITLE:
BukitTimahTutor School/Track Map + Registry Spec v1.0 (ILT × InterstellarCore × ChronoFlight)
SLUG:
bukit-timah-school-map-registry-spec-v1-0
VERSION:
BT_SCHOOL_MAP_REG_v1_0
PARENT:
BT_ICF_CORRIDOR_CTW_v1_0
BT.EDU.Z1.S.CTW.COR.ICF.001
PURPOSE:
Represent Bukit Timah’s real education corridor as machine-readable nodes + edges:
Kindergarten → Primary → PSLE → PG selection → Secondary (Full SBB) → IP/IB/Intl/JC/Poly/ITE
→ University → Career, with travel/time/buffer binds.
COORDINATE GRAMMAR (LOCK):
<REGION>.<LANE>.Z<ZOOM>.<ROLE>.<TYPE>.<ID>
ZOOM:
Z2 = institution nodes (schools + programmes)
Z6 = national gate nodes (PSLE/SEC/etc.)
Z1 = tuition execution nodes (BukitTimahTutor)
Z0 = learner micro-skill nodes (subject-specific control towers)
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A) NODE TYPES (TYPE ENUM)
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TYPE ENUM (stable):
- N.SCH.KDG     # Kindergarten school node
- N.SCH.PRI     # Primary school node
- N.SCH.SEC     # Secondary school node
- N.SCH.PST     # Post-secondary node (JC/Poly/ITE)
- N.SCH.UNI     # University node
- N.TRK.IP      # Integrated Programme track node (secondary→JC integrated)
- N.TRK.IB      # IB track node
- N.TRK.INTL    # International school track node
- N.TRK.FSBB    # Full SBB profile node (G1/G2/G3 subject levels)
- N.SVC.TUI     # Tuition support node (BukitTimahTutor)
- N.GEO.AREA    # Area cluster node (Bukit Timah sub-areas; optional)
- B.TRN.MRT     # Transport bind (MRT)
- B.TRN.BUS     # Transport bind (bus)
- B.FAM.TTC     # Family time-to-class bind (TTC)
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B) SCHOOL NODE RECORD (schema)
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NodeRecord.School = {
  Coord: "BT.EDU.Z2.N.SCH.<KDG|PRI|SEC|PST|UNI>.<ID>",
  NameOfficial: "<official name>",
  NameAliases: ["<common alias>", "<legacy name>", "<abbrev>"],
  AddressHint: "<optional, coarse>",
  ProgrammeTags: ["FullSBB", "IP", "IB", "Intl", "OLevel/SEC", "JC", "Poly", "ITE"],
  SubjectLevelSupport: { "G1": true/false, "G2": true/false, "G3": true/false },   # for Secondary
  LoadProfile: { "HomeworkLoad": L/M/H, "CCAIntensity": L/M/H, "ExamDensity": L/M/H },
  TravelBinds: ["BT.TRN.Z2.B.MRT.DTL.06A", "BT.TRN.Z2.B.MRT.DTL.07A", "BT.TRN.Z2.B.BUS.<ID>"],
  BufferRisks: ["late_night", "travel_friction", "overlap_exam_weeks"],
  Notes: "<short, operator-facing>"
}
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C) TRACK NODE RECORD (schema)
----------------------------------------
NodeRecord.Track = {
  Coord: "BT.EDU.Z2.N.TRK.<IP|IB|INTL|FSBB>.<ID>",
  EntryGate: "SG.EDU.Z6.N.GATE.<PSLE|PG|SEC|PST|UNI>.001",
  ExitGate:  "SG.EDU.Z6.N.GATE.<PST|UNI|CAR>.001",
  InvariantEmphasis: ["transfer", "writing_rent", "project_rent", "proof_rent", "timed_truth"],
  Notes: "<what changes in the corridor; do not sell, just describe>"
}
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D) EDGE TYPES (RELATIONS)
----------------------------------------
EdgeType ENUM (stable):
- feeds_to         # institution progression: KDG→PRI→SEC→PST→UNI
- gates_to         # gate selection: PRI→PSLE→PG; SEC→PST; etc.
- track_forks_to   # SEC→IP/IB/Intl/JC/Poly/ITE forks
- commute_bind     # student/household→school travel friction bind
- tuition_supports # BukitTimahTutor supports this school/track (non-exclusive)
- buffer_couples   # school load couples to household buffer (sleep/time/Δt_b)
EdgeRecord = {
  From: "<Coord>",
  To: "<Coord>",
  Type: "<EdgeType>",
  Weight: 0.0..1.0,                # strength of coupling (default 0.5)
  Notes: "<short>"
}
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E) ALIAS REGISTRY (critical for search + ingestion)
----------------------------------------
AliasRecord = {
  EntityCoord: "<Coord>",
  Alias: "<string>",
  AliasType: "<official|common|legacy|abbrev|misspelling>",
  Confidence: 0.0..1.0
}
RULE:
Never overwrite official names; add aliases forward-only.
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F) POPULATION METHOD (how to fill without breaking canon)
----------------------------------------
Step 1: Create AreaCluster nodes (optional):
BT.EDU.Z2.N.GEO.AREA.<ID>  (e.g., “SixthAve”, “TanKahKee”, “UpperBukitTimah”)
Step 2: Add School nodes for Bukit Timah catchment (KDG/PRI/SEC) + major PostSec/Uni nodes.
Step 3: Attach Travel binds (MRT/bus) and TTC bind sensors (family).
Step 4: Add edges:
- KDG feeds_to PRI
- PRI gates_to PSLE
- PSLE gates_to PG selection
- PG gates_to Secondary corridor
- Secondary gates_to SEC
- SEC track_forks_to PostSec options
- PostSec gates_to Uni
- Uni gates_to Career
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G) REALITY CHECK (metaphor vs mechanism)
----------------------------------------
Metaphor:
“Flight path / control tower” language.
Mechanism:
- Nodes = institutions/gates
- Edges = progression and coupling
- Sensors = timed truth, transfer, buffer, TTC friction, debt (Δt_b)
- Actions = truncate+stitch repairs + verified landings + maintenance returns
VERSION LOCK:
BT_SCHOOL_MAP_REG_v1_0 (forward-only)
END.

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CHILD PACK 2/3 — GATE PLAYBOOKS v1.0 (ILT × CF × InterstellarCore)
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TITLE:
BukitTimahTutor Gate Playbooks v1.0 (PSLE → PG → SEC → PostSec → Uni → Career)
SLUG:
bukit-timah-gate-playbooks-v1-0
VERSION:
BT_GATE_PLAYBOOKS_v1_0
PARENT:
BT_ICF_CORRIDOR_CTW_v1_0
BT.EDU.Z1.S.CTW.COR.ICF.001
COMMON FORMAT (every gate uses same template):
GatePlaybook = {
  GateCoord,
  Purpose,
  Inputs,
  Outputs,
  GateConditions (what “landing proof” means here),
  ILT Ledger (Top 10 invariants),
  ChronoFlight Near-Node Rules (τ, A, B, Θ, Δt_b),
  Failure Trace (Z0→Z2→P drop),
  Repair Corridor (truncate+stitch),
  Weekly Output Contract (what must be produced),
  Parent Envelope Actions (buffer/TTC)
}
----------------------------------------
GATE 1 — PSLE (Primary → Secondary selection gate)
----------------------------------------
GateCoord:
SG.EDU.Z6.N.EXM.PSLE.001
Purpose (non-sales):
Assess attainment at end of primary education against Primary Mathematics objectives.
GateConditions (landing proof):
- Must land under exact paper constraints (timed + no-calc vs calc)
- Must show awardable working where required
- Must maintain accuracy under switching and fatigue
ILT Ledger (Top 10 invariants):
1) Read → represent (model/diagram/units) before compute
2) Unit consistency and required-unit answers
3) Estimation sanity check (order of magnitude)
4) Bar-model / representation correctness (when used)
5) Method selection is explicit (why this operation)
6) Arithmetic accuracy (no-calc integrity for Paper 1)
7) Working is awardable (steps visible)
8) Switching control (no “carry-over method” error)
9) Error tagging (concept/method/representation/careless)
10) Retest schedule is obeyed (D+1/D+3/D+7)
ChronoFlight near-node rules:
- As τ shrinks: stop breadth expansion; increase landings; protect buffer
- If Θ < 1: emergency truncate+stitch only (top 2 buckets)
- Debt rule: do not borrow sleep to “finish papers” (Δt_b increases future collapse)
Weekly Output Contract (Final approach):
- 1 Paper 1 landing (no-calc) + strict marking
- 1 Paper 2 slice landing (structured) + working rent enforced
- 3 maintenance returns (5–12 min, retrieval-first)
- 1 rewrite of weakest solution (awardability training)
----------------------------------------
GATE 2 — PG Selection (PG1 / PG2 / PG3 posting corridor gate)
----------------------------------------
GateCoord:
SG.EDU.Z6.N.GATE.PG.001
Purpose:
Route learner into a secondary corridor band; prevent identity collapse and drift spiral.
GateConditions (landing proof):
- Learner can operate stably in chosen corridor band (P2→P3 target)
- Lane stability matters more than prestige
ILT Ledger (Top 10 invariants):
1) Corridor truth > ego truth (choose what you can sustain)
2) Maintain daily maintenance (small returns > big bursts)
3) Representation invariants remain unchanged across corridors
4) Timed truth begins (short landings weekly)
5) “No prompt dependency” rule (self-start)
6) Checking routine installed (units/estimation)
7) Avoidance onset is treated as sensor, not character flaw
8) Debt control: protect sleep buffer before increasing workload
9) Two-bucket repair rule (do not chase everything)
10) Transfer practice exists weekly (variation ladder)
ChronoFlight rules:
- Immediately after gate: τ resets (new runway). Use it to widen exits (A↑).
- If placement disappointment raises N (noise): reduce load, restore signal.
Weekly Output Contract:
- 1 baseline diagnostic landing (timed mini)
- 1 transfer ladder
- 3 micro-maintenance returns
- 1 parent envelope action (schedule friction reduction)
----------------------------------------
GATE 3 — SEC (Full SBB G1/G2/G3 subject-level exam gate)
----------------------------------------
GateCoord:
SG.EDU.Z6.N.EXM.SEC.001
Purpose:
Certify subject outcomes at subject level (G1/G2/G3) under SEC.
GateConditions (landing proof):
- Stable performance at the subject level taken
- Timed truth dominates; “homework stability” is not enough
- Mixed-level subject load must remain inside buffer envelope
ILT Ledger (Top 10 invariants):
1) Timed landings weekly (paper slices)
2) Method selection under switching (mixed sets)
3) Working rent (awardable steps where required)
4) Error clustering elimination (ECI trending down)
5) Transfer ratio rising (variants survive)
6) Audit routine reflex (catch before submission)
7) Pace budget management (PB)
8) Buffer protection (sleep + recovery)
9) Near-node debt ban (no last-minute topic binge)
10) Retest schedule enforced (D+1/D+3/D+7)
ChronoFlight near-node rules:
- SEC is a near-node gate: as τ→0, exits close; wrong decisions look “reasonable”
- If Θ < 1: truncate+stitch only; top-2 bucket repairs; increase landings
Weekly Output Contract (final approach):
- 1 timed slice landing per subject (or per priority subject)
- 1 mixed-switching set
- 3 maintenance returns
- 1 strict-mark rewrite of weakest solution
----------------------------------------
GATE 4 — Post-Secondary Selection (IP/IB/Intl/JC/Poly/ITE routing)
----------------------------------------
GateCoord:
SG.EDU.Z6.N.GATE.PST.001
Purpose:
Route to a survivable next-stage corridor with future mobility.
GateConditions:
- Academic corridor fit + buffer fit
- Ability to sustain the mode of learning required (exam-heavy vs project-heavy)
ILT Ledger (Top 10 invariants):
1) Corridor fit is a stability decision
2) Transfer is compulsory (new mode requires adaptation)
3) Self-ILT begins (student keeps their own ledger)
4) Work quality must be reproducible (not one-off)
5) Project/assignment “rent” is paid (planning + drafts + submission discipline)
6) Exam rent is paid (timed practice if exam-heavy)
7) Attention and schedule are controlled (TTC + friction)
8) Two-bucket repair rule persists
9) Buffer protection is non-negotiable
10) Exit aperture planning (keep options open with fundamentals)
ChronoFlight:
- Choose corridors that increase A (exit aperture) over time, not shrink it.
----------------------------------------
GATE 5 — University Selection
----------------------------------------
GateCoord:
SG.EDU.Z6.N.GATE.UNI.001
Purpose:
Route into a domain corridor; prepare for higher autonomy and depth.
ILT Ledger (Top 10 invariants):
1) Independent learning loop (plan→study→test→repair)
2) Evidence of depth (not just grades)
3) Communication rent (writing, explanation, proof of work)
4) Project rent (deliverables + iteration)
5) Transfer across contexts
6) Buffer + health protection
7) Time debt visibility (Δt_b tracked)
8) Consistency beats bursts
9) Networks/mentors as repair accelerators
10) Artefact return (notes, systems, templates)
----------------------------------------
GATE 6 — Career Entry / Role-Fit Gate
----------------------------------------
GateCoord:
SG.CAR.Z6.N.GATE.001
Purpose:
Stabilise performance in a role corridor (Operator/Visionary/Architect mix) without burnout.
ILT Ledger (Top 10 invariants):
1) Deliverables are reproducible
2) Feedback is integrated (fast repair)
3) Communication is precise (English V3.0 where needed)
4) Work is valid (VeriWeft: no “fake” output)
5) Buffer is protected (burnout = collapse valley)
6) Skill maintenance returns exist (continuous upskilling)
7) Transfer into new tools/AI is controlled (ρ below capacity)
8) Risk management (stop-loss actions)
9) Artefact building (templates, checklists, systems)
10) Corridor widening (keep A from collapsing)
VERSION LOCK:
BT_GATE_PLAYBOOKS_v1_0 (forward-only)
END.

================================================================================
CHILD PACK 3/3 — ONE-PANEL DASHBOARD TEMPLATE v1.0
================================================================================
TITLE:
BukitTimahTutor One-Panel ILT × InterstellarCore × ChronoFlight Dashboard v1.0
(Reusable per learner, per subject, per gate)
SLUG:
bukit-timah-one-panel-ilt-interstellarcore-chronoflight-dashboard-v1-0
VERSION:
BT_ONE_PANEL_ICF_v1_0
PARENT:
BT_ICF_CORRIDOR_CTW_v1_0
USAGE:
Copy this panel into each learner file. Update weekly.
----------------------------------------
A) IDENTITY + ROUTE
----------------------------------------
LearnerID:
Stage:
{KDG | PRI(P1–P6) | PSLE | PG | SEC | IP | IB | INTL | JC | POLY | ITE | UNI | CAR}
CurrentNode:
BT.EDU.Z2.N.SCH.<...>.<ID>
NextGate:
SG.EDU.Z6.N.<...>.001
----------------------------------------
B) CHRONOFLIGHT STATE X(k) (weekly)
----------------------------------------
τ (weeks to next gate):
A (exit aperture 0–5):
B (buffer 0–5):
Δt_b (time debt 0–5):
TruthClarity = S/(S+N):
RouteState: {climb | stable | drift | corrective | descent}
Phase: {P0 | P1 | P2 | P3}
Θ (irreversibility ratio):
Λ (enforcement lag ratio):
Interpretation (one line):
<what is happening, mechanically>
----------------------------------------
C) EVIDENCE (TIMED TRUTH + TRANSFER)
----------------------------------------
TimedLandingScore:
TransferScore:
RepeatBucketIndex (ECI):
AvoidanceOnset (AO): {none | mild | high}
If PSLE:
- Paper1_NoCalcScore
- Paper2_StructuredScore
If SEC:
- SubjectLevel (G1/G2/G3)
- SliceLandingScore
----------------------------------------
D) ILT LEDGER (TOP 10 INVARIANTS — THIS WEEK)
----------------------------------------
InvariantLedgerTop10:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
BreachListTop3 (with bucket tags):
- B1: <concept|method|representation|careless|speed|stress|working_rent>
- B2: ...
- B3: ...
----------------------------------------
E) REPAIR QUEUE (TRUNCATE + STITCH)
----------------------------------------
Top2RepairBuckets (ONLY):
- Bucket_A:
  Z0 micro-repair: <what exactly>
  Landing proof: <timed mini / slice>
  Retests: D+1 / D+3 / D+7
- Bucket_B:
  ...
MaintenanceReturns Scheduled:
- D+1:
- D+3:
- D+7:
- D+14:
- D+30:
----------------------------------------
F) WEEK CONTRACT (OUTPUTS)
----------------------------------------
Must-Produce:
- 1 timed landing (right format for stage)
- 1 transfer ladder
- 3 maintenance returns
- 1 rewrite of weakest solution (awardability / working rent) [P5+ recommended; SEC mandatory]
----------------------------------------
G) PARENT / HOUSEHOLD ENVELOPE (BT TTC + BUFFER)
----------------------------------------
SleepBand: <hours + consistency>
TTC_Friction: <low/med/high>  (travel + schedule + meals)
OverloadFlag: <on/off> (too many competing loads)
Action (one line): <reduce friction / protect slots / trim overload>
VERSION LOCK:
BT_ONE_PANEL_ICF_v1_0
END.

================================================================================
SIMULATION PACK v1.0 — 5 LEARNERS × 12 WEEKS → PSLE GATE
(STRICT ONE-PANEL LOGS, COMPRESSED FORMAT)
================================================================================
GATE:
SG.EDU.Z6.N.EXM.PSLE.001
STAGE:
PSLE (Final Approach)
COMMON ILT LEDGER (PSLE-ILT-10)  [same for all learners; referenced in weekly logs]
1) Read → Represent (model/diagram/units) before compute
2) Units + required form (final answer format)
3) Estimation sanity check (order of magnitude)
4) Bar model / representation correctness (if used)
5) Method choice stated (“why this operation”)
6) No-calc integrity (Paper 1 discipline)
7) Working is awardable (steps visible)
8) Switching control (don’t reuse wrong method)
9) Error tagging bucket is explicit
10) Retest schedule obeyed (D+1/D+3/D+7)
WEEK INDEX:
W12 → W1 (τ=12→1 weeks to PSLE)
(PSLE occurs after W1)
SCORES:
P1 = Paper 1 (No Calculator) landing score
P2 = Paper 2 (Calculator allowed; structured) landing score
ECI = RepeatBucketIndex (0–1; lower is better)
AO = Avoidance onset (none/mild/high)
STATE:
A=ExitAperture (0–5), B=Buffer (0–5), Δt_b=TimeDebt (0–5)
TruthClarity=S/(S+N) (0–1)
Θ=Irreversibility ratio (≥1 ok; <1 emergency)
Λ=Enforcement lag ratio (lower better)
RULE:
If Θ < 1 → EMERGENCY MODE (truncate+stitch only; TOP-2 buckets; stop breadth)
================================================================================
STUDENT A — “Stable Operator” (consistent, low noise, good buffer)
LearnerID: BT_SIM_A
CurrentNode: BT.EDU.Z2.N.SCH.PRI.A001
NextGate: SG.EDU.Z6.N.EXM.PSLE.001
================================================================================
W12 | τ12 A4 B4 Δt_b0 Truth0.78 PhaseP3 Route=stable Θ1.6 Λ0.6 | P1=78 P2=76 ECI0.22 AO=none
     BreachTop3: (careless-units),(representation-label),(switching-slip)
     Top2Repairs: AC_p units-check; MF/RE label-before-compute | Outputs: P1 slice + P2 slice; D+1/D+3/D+7; rewrite weakest
W11 | τ11 A4 B4 Δt_b0 Truth0.79 P3 stable Θ1.6 Λ0.6 | P1=80 P2=78 ECI0.20 AO=none
     Top2Repairs: AC_p estimation-check; switching-control | Parent: keep sleep band fixed
W10 | τ10 A4 B4 Δt_b0 Truth0.80 P3 stable Θ1.5 Λ0.6 | P1=82 P2=79 ECI0.18 AO=none
     Top2Repairs: method-choice-statement; working-awardability | Output: strict marking + rewrite
W9  | τ9  A4 B4 Δt_b0 Truth0.81 P3 stable Θ1.5 Λ0.6 | P1=83 P2=80 ECI0.17 AO=none
     Top2Repairs: representation-first; careless subtraction | D+1 retest passed
W8  | τ8  A4 B4 Δt_b0 Truth0.82 P3 stable Θ1.4 Λ0.6 | P1=84 P2=81 ECI0.16 AO=none
     Top2Repairs: multi-step order; units-final-line | Parent: protect weekend landing slot
W7  | τ7  A4 B4 Δt_b0 Truth0.83 P3 stable Θ1.4 Λ0.5 | P1=85 P2=82 ECI0.14 AO=none
     Top2Repairs: switching trap; bar-model accuracy | Output: Paper1 full weekly begins
W6  | τ6  A4 B4 Δt_b0 Truth0.84 P3 stable Θ1.3 Λ0.5 | P1=86 P2=83 ECI0.13 AO=none
     Top2Repairs: working-rent clarity; estimation | D+3/D+7 returns clean
W5  | τ5  A4 B4 Δt_b0 Truth0.85 P3 stable Θ1.3 Λ0.5 | P1=87 P2=84 ECI0.12 AO=none
     Top2Repairs: careless decimals; diagram labels
W4  | τ4  A4 B4 Δt_b0 Truth0.86 P3 stable Θ1.2 Λ0.5 | P1=88 P2=85 ECI0.11 AO=none
     Top2Repairs: speed consistency; final-line format
W3  | τ3  A4 B4 Δt_b0 Truth0.87 P3 stable Θ1.2 Λ0.5 | P1=89 P2=86 ECI0.10 AO=none
     Top2Repairs: micro-careless; switching | Output: full P2 bi-weekly → weekly
W2  | τ2  A4 B4 Δt_b0 Truth0.88 P3 stable Θ1.1 Λ0.5 | P1=90 P2=87 ECI0.09 AO=none
     Top2Repairs: none major; maintain returns only
W1  | τ1  A4 B4 Δt_b0 Truth0.88 P3 stable Θ1.1 Λ0.4 | P1=90 P2=88 ECI0.08 AO=none
     Contract: landings only; no novelty
END STATE (expected): PSLE strong, low variance, high survivability.
================================================================================
STUDENT B — “TTC Friction + Avoidance” (envelope-sensitive; gains if buffer fixed)
LearnerID: BT_SIM_B
CurrentNode: BT.EDU.Z2.N.SCH.PRI.B001
NextGate: SG.EDU.Z6.N.EXM.PSLE.001
================================================================================
W12 | τ12 A3 B2 Δt_b2 Truth0.60 PhaseP2 Route=drift Θ1.1 Λ0.9 | P1=62 P2=66 ECI0.38 AO=mild
     BreachTop3: (no-calc slips),(missing model),(careless)
     Top2Repairs: NF no-calc drill; MF/RE model-first | Parent: reduce TTC friction (travel+meals)
W11 | τ11 A3 B2 Δt_b2 Truth0.61 P2 drift Θ1.1 Λ0.9 | P1=64 P2=66 ECI0.36 AO=mild
     Top2Repairs: AC_p checking checklist; units | Output: shorter but consistent returns
W10 | τ10 A3 B2 Δt_b3 Truth0.56 P1 Route=descent Θ0.9 Λ1.1 | P1=58 P2=63 ECI0.40 AO=high
     EMERGENCY: Θ<1 → truncate+stitch only; stop breadth; shorten tasks
     Top2Repairs: Paper1 no-calc integrity; representation before compute | Parent: enforce sleep band
W9  | τ9  A3 B2 Δt_b3 Truth0.58 P1 corrective Θ0.95 Λ1.0 | P1=60 P2=64 ECI0.37 AO=high
     Top2Repairs: careless tagging; bar-model lab | Output: 1 landing only + 3 returns
W8  | τ8  A3 B3 Δt_b2 Truth0.62 P2 corrective Θ1.05 Λ0.9 | P1=64 P2=66 ECI0.34 AO=mild
     Buffer restored (B↑, Δt_b↓). Continue top-2 only.
W7  | τ7  A3 B3 Δt_b2 Truth0.64 P2 stable Θ1.05 Λ0.9 | P1=66 P2=68 ECI0.32 AO=mild
     Top2Repairs: switching traps; units | Parent: keep routine unchanged
W6  | τ6  A3 B3 Δt_b2 Truth0.66 P2 stable Θ1.00 Λ0.9 | P1=68 P2=70 ECI0.30 AO=mild
     Near-node tightening begins; no new topic chases
W5  | τ5  A3 B3 Δt_b2 Truth0.67 P2 stable Θ1.00 Λ0.8 | P1=69 P2=71 ECI0.28 AO=none
     Top2Repairs: Paper1 stamina; checking routine
W4  | τ4  A3 B3 Δt_b2 Truth0.68 P2 stable Θ0.95 Λ0.9 | P1=68 P2=72 ECI0.27 AO=mild
     EMERGENCY-lite: Θ borderline → tighten to landings+returns only
W3  | τ3  A3 B3 Δt_b1 Truth0.70 P2 corrective Θ1.00 Λ0.8 | P1=70 P2=73 ECI0.25 AO=none
     Top2Repairs: no-calc accuracy; final answer form
W2  | τ2  A3 B3 Δt_b1 Truth0.71 P2 stable Θ1.00 Λ0.8 | P1=71 P2=74 ECI0.24 AO=none
W1  | τ1  A3 B3 Δt_b1 Truth0.71 P2 stable Θ0.95 Λ0.8 | P1=71 P2=74 ECI0.23 AO=none
     Contract: keep buffer; don’t spike workload
END STATE (expected): PSLE moderate/stable; outcome depends heavily on envelope control.
================================================================================
STUDENT C — “Late Bloomer” (low start, high RepairRate when routed correctly)
LearnerID: BT_SIM_C
CurrentNode: BT.EDU.Z2.N.SCH.PRI.C001
NextGate: SG.EDU.Z6.N.EXM.PSLE.001
================================================================================
W12 | τ12 A3 B3 Δt_b1 Truth0.52 PhaseP1 Route=corrective Θ1.2 Λ0.7 | P1=55 P2=60 ECI0.46 AO=none
     BreachTop3: (fractions ladder),(model errors),(method confusion)
     Top2Repairs: FL part-whole+equivalence; MF bar-model invariants
W11 | τ11 A3 B3 Δt_b1 Truth0.56 P2 corrective Θ1.2 Λ0.7 | P1=58 P2=62 ECI0.42 AO=none
W10 | τ10 A3 B3 Δt_b1 Truth0.60 P2 climb Θ1.2 Λ0.7 | P1=62 P2=65 ECI0.37 AO=none
     Top2Repairs: Paper1 no-calc basics; representation labels
W9  | τ9  A3 B3 Δt_b1 Truth0.64 P2 climb Θ1.2 Λ0.6 | P1=66 P2=69 ECI0.32 AO=none
     First true timed landings pass (signal rises, noise falls)
W8  | τ8  A3 B3 Δt_b1 Truth0.68 P2 stable Θ1.2 Λ0.6 | P1=70 P2=72 ECI0.28 AO=none
     Top2Repairs: switching; careless reduction of fractions
W7  | τ7  A4 B3 Δt_b1 Truth0.72 PhaseP3 Route=climb Θ1.3 Λ0.6 | P1=74 P2=76 ECI0.23 AO=none
     Exit aperture widens (A↑): options open because stability is real
W6  | τ6  A4 B3 Δt_b1 Truth0.75 P3 stable Θ1.2 Λ0.6 | P1=76 P2=78 ECI0.20 AO=none
W5  | τ5  A4 B3 Δt_b1 Truth0.78 P3 stable Θ1.2 Λ0.6 | P1=78 P2=80 ECI0.18 AO=none
     Top2Repairs: working awardability; final-line format
W4  | τ4  A4 B3 Δt_b1 Truth0.80 P3 stable Θ1.1 Λ0.6 | P1=80 P2=82 ECI0.16 AO=none
W3  | τ3  A4 B3 Δt_b1 Truth0.82 P3 stable Θ1.1 Λ0.6 | P1=82 P2=83 ECI0.14 AO=none
W2  | τ2  A4 B3 Δt_b1 Truth0.83 P3 stable Θ1.1 Λ0.5 | P1=83 P2=84 ECI0.13 AO=none
W1  | τ1  A4 B3 Δt_b1 Truth0.84 P3 stable Θ1.0 Λ0.5 | P1=84 P2=85 ECI0.12 AO=none
     Contract: landings only; keep returns
END STATE (expected): strong jump; “late bloomer” finishes strong due to high R.
================================================================================
STUDENT D — “Self-ILT / High Reasoning” (great modeling, undertrained timing initially)
LearnerID: BT_SIM_D
CurrentNode: BT.EDU.Z2.N.SCH.PRI.D001
NextGate: SG.EDU.Z6.N.EXM.PSLE.001
================================================================================
W12 | τ12 A4 B3 Δt_b1 Truth0.80 PhaseP3 Route=stable Θ1.4 Λ0.6 | P1=75 P2=84 ECI0.20 AO=none
     BreachTop3: (Paper1 pace),(no-calc slips),(over-writing time loss)
     Top2Repairs: PB_p Paper1 pacing; NC_p no-calc discipline
W11 | τ11 A4 B3 Δt_b1 Truth0.81 P3 stable Θ1.4 Λ0.6 | P1=76 P2=84 ECI0.19 AO=none
W10 | τ10 A4 B3 Δt_b1 Truth0.82 P3 stable Θ1.3 Λ0.6 | P1=78 P2=85 ECI0.18 AO=none
     Intervention: “timed Paper1 weekly” rule enforced
W9  | τ9  A4 B3 Δt_b1 Truth0.83 P3 climb Θ1.3 Λ0.6 | P1=80 P2=85 ECI0.17 AO=none
W8  | τ8  A4 B3 Δt_b1 Truth0.84 P3 climb Θ1.3 Λ0.6 | P1=82 P2=86 ECI0.16 AO=none
W7  | τ7  A4 B3 Δt_b1 Truth0.85 P3 stable Θ1.2 Λ0.6 | P1=83 P2=86 ECI0.15 AO=none
W6  | τ6  A4 B3 Δt_b1 Truth0.86 P3 stable Θ1.2 Λ0.5 | P1=84 P2=87 ECI0.14 AO=none
W5  | τ5  A4 B3 Δt_b1 Truth0.86 P3 stable Θ1.1 Λ0.5 | P1=85 P2=87 ECI0.13 AO=none
W4  | τ4  A4 B3 Δt_b1 Truth0.87 P3 stable Θ1.1 Λ0.5 | P1=86 P2=88 ECI0.12 AO=none
W3  | τ3  A4 B3 Δt_b1 Truth0.87 P3 stable Θ1.1 Λ0.5 | P1=87 P2=88 ECI0.11 AO=none
W2  | τ2  A4 B3 Δt_b1 Truth0.88 P3 stable Θ1.0 Λ0.5 | P1=88 P2=88 ECI0.10 AO=none
W1  | τ1  A4 B3 Δt_b1 Truth0.88 P3 stable Θ1.0 Λ0.5 | P1=88 P2=89 ECI0.10 AO=none
END STATE (expected): very strong, especially Paper 2; timing fix makes Paper 1 catch up.
================================================================================
STUDENT E — “GeniusCorridor Candidate” (high ceiling, high volatility, buffer thin)
LearnerID: BT_SIM_E
CurrentNode: BT.EDU.Z2.N.SCH.PRI.E001
NextGate: SG.EDU.Z6.N.EXM.PSLE.001
================================================================================
W12 | τ12 A4 B2 Δt_b2 Truth0.84 PhaseP3 Route=climb Θ1.2 Λ0.7 | P1=82 P2=88 ECI0.24 AO=none
     BreachTop3: (careless),(speed overaccuracy),(sleep borrowing)
     Top2Repairs: AC_p slow-down checkpoint; Parent: protect buffer
W11 | τ11 A4 B2 Δt_b3 Truth0.78 PhaseP2 Route=drift Θ1.0 Λ0.9 | P1=74 P2=86 ECI0.30 AO=mild
     Cause: Δt_b spike (frontier overload) → noise rises, signal drops
     Top2Repairs: sleep restore; Paper1 no-calc discipline
W10 | τ10 A4 B1 Δt_b4 Truth0.70 PhaseP1 Route=descent Θ0.8 Λ1.2 | P1=66 P2=82 ECI0.36 AO=high
     EMERGENCY: Θ<1 → shut GeniusCorridor; landings + returns only
     Top2Repairs: buffer rebuild; careless bucket elimination
W9  | τ9  A3 B2 Δt_b3 Truth0.74 PhaseP2 Route=corrective Θ0.95 Λ1.0 | P1=72 P2=84 ECI0.30 AO=mild
     Parent envelope action: hard sleep band + remove extra enrichment temporarily
W8  | τ8  A4 B2 Δt_b2 Truth0.80 PhaseP3 Route=climb Θ1.1 Λ0.8 | P1=78 P2=86 ECI0.24 AO=none
W7  | τ7  A4 B2 Δt_b2 Truth0.82 P3 stable Θ1.1 Λ0.7 | P1=80 P2=87 ECI0.22 AO=none
W6  | τ6  A4 B2 Δt_b2 Truth0.83 P3 stable Θ1.0 Λ0.7 | P1=81 P2=87 ECI0.21 AO=none
W5  | τ5  A4 B2 Δt_b2 Truth0.84 P3 stable Θ1.0 Λ0.7 | P1=82 P2=88 ECI0.20 AO=none
W4  | τ4  A4 B2 Δt_b3 Truth0.79 PhaseP2 Route=drift Θ0.9 Λ0.9 | P1=76 P2=86 ECI0.26 AO=mild
     EMERGENCY-lite: debt creeping back → tighten again (no novelty)
W3  | τ3  A4 B3 Δt_b2 Truth0.83 PhaseP3 Route=corrective Θ1.0 Λ0.7 | P1=82 P2=88 ECI0.20 AO=none
W2  | τ2  A4 B3 Δt_b2 Truth0.84 P3 stable Θ1.0 Λ0.7 | P1=83 P2=88 ECI0.19 AO=none
W1  | τ1  A4 B3 Δt_b2 Truth0.85 P3 stable Θ1.0 Λ0.6 | P1=84 P2=89 ECI0.18 AO=none
     Contract: landings only; keep buffer thick; no late frontier
END STATE (expected): strong but variance-sensitive; outcome depends on buffer enforcement.
================================================================================
COMPARATIVE OUTCOME SNAPSHOT (WHY THEY DIVERGED)
================================================================================
A: stayed P3 because B high, Δt_b low → exits stayed open (A high) → steady climb.
B: envelope-sensitive; short periods of Θ<1 created emergency weeks → moderate stable finish when buffer restored.
C: high RepairRate once routed correctly → drift reversed early enough → P3 by W7.
D: already high signal; main weakness was Paper1 timing → fixed by enforced timed landings.
E: highest ceiling but debt spikes collapse TruthClarity → required “GeniusCorridor shutdown” to protect base P3.
END SIMULATION PACK.